1. Field of the Invention
The present invention relates to an integrated inductance in a monolithic circuit. More specifically, it relates to an integrated inductance in a monolithic circuit including a limited number of passive elements such as inductors, resistors or capacitors, and possibly a limited number of active elements, such as a protection diode.
2. Discussion of the Related Art
FIG. 1 shows a cross-section of a conventional monolithic circuit including, as an example, an inductance 10, a resistor 11, and a capacitor 12. Only three metallization levels are shown in FIG. 1. The monolithic circuit could possibly include one or several additional metallization levels.
A semiconductor substrate 13, for example, silicon, is covered with a multiple-layer of a first, second, and third insulating layers 14, 15, and 16, respectively. The first insulating layer may be formed in silicon oxide, and the second and third insulating layers 15, 16, in a material with a small dielectric coefficient, for example, benzo-cyclo-butene (BCB). Substrate 13 may be formed of an isolating material, for example, glass, first insulating layer 14 being then not necessary. As an example, the second and third insulating layers 15, 16 have a thickness of approximately 10 μm, and a dielectric coefficient on the order of 2.6.
Inductance 10 includes a conductive spiral 20, for example, made of copper, belonging to the second metallization level and resting on the external surface of second insulating layer 15. Resistor 11 and capacitor 12 are formed on first insulating layer 14.
FIG. 2 shows a top view at the level of inductance 10 of the second metallization level. Spiral 20 includes a first end 21 at the spiral border, which extends in a first connection track 22 connected to a pad 23 (see FIG. 1). Pad 23 may belong to a pad assembly, formed in the third metallization level, intended, for example, for the direct assembly of the upper surface of the monolithic circuit on a printed circuit.
As illustrated in FIGS. 1 and 2, a second end 24, substantially located at the center of spiral 20, is connected to a second connection track 26, formed of a metal of the second metallization level. The connection between second end 24 and second connection track 26 is performed via a connecting track 29 formed of a metal, for example, aluminum, of the first metallization deposited on first insulating layer 14. Connecting track 29 is connected at its two ends respectively to second end 24 of spiral 20 and to second connection track 26 by two vias 27, 28 formed in second insulating layer 15.
First connection track 26 performs the connection between inductance 10 and resistor 11. First connection track 26 is connected by a via 30 crossing the second insulating layer 15 to a first terminal 31 of resistor 11. First terminal 31 is connected to a second terminal 32 of resistor 11 by a resistive strip 33, for example, tantalum nitride (TaN), deposited on first insulating layer 14 and covered with an insulating layer, for example, silicon oxide 35, covered with a silicon nitride layer 36. At the level of each terminal 31, 32 of resistor 11, metal portions 37, 38, especially aluminum, are interposed between terminals 32, 31 of resistor 11 and of first insulating layer 14. Second terminal 32 of resistor 11 is connected to a third connection track 40, including a metal strip, for example, copper, of the second metallization level, by a via 41 crossing second insulating layer 15.
Third connection track 40 connects resistor 11 to capacitor 12. Third connection track 40 is connected to a first plate 45 of capacitor 12, by a via 46 crossing second insulating layer 15. First plate 45 is for example made of tantalum nitride (TaN) covering a metal strip 47, for example, aluminum, of the first metallization level. Second plate 48 of capacitor 12 is separated from first plate 45 by a silicon nitride layer 49. Silicon nitride layer 49 covers the entire first plate 45, an insulating area 51, for example, silicon oxide, being interposed between silicon nitride layer 49 and first plate 45, except for the area where the two plates 45, 48 face each other. Second plate 48 is formed in a metal, for example, copper, of the second metallization level deposited on silicon nitride layer 49 at the level of an opening formed in second insulating layer 15. Second plate 48 extends in a fourth connection track 52, deposited on second insulating layer 15, and is connected to a pad 55.
As shown in FIG. 2, a ground plane 56 surrounds spiral 20 of inductance 10. Ground plane 56 also surrounds the first 22, second 26, third 40, and fourth 52 connection tracks. Ground plane 56 improves the quality factor of the monolithic circuit at high frequencies, since it enables obtaining interconnections of coplanar waveguide type (CPW), which enables performing impedance matchings if necessary and ensuring an electromagnetic isolation between the components and the metallizations of the monolithic circuit.
The fact that connecting track 29 is formed by a metal strip of the first metallization level has several disadvantages.
Connecting track 29 adds a stray capacitance due to the coupling with substrate 13, even when substrate 13 is glass.
Further, connecting track 29 behaves as a parasitic series resistor, which can become significant at high frequencies. A deterioration of the behavior of inductance 10 with frequency can then be acknowledged.
Further, the presence of connecting track 29 on first insulating layer 14 causes the forming, if expensive leveling steps are not carried out, of significant drops, currently called “steps”, on the upper surface of second insulating layer 15. The manufacturing method of inductance 10 on the uneven upper surface of second insulating layer 15 is then more complex. Further, a significant dispersion of some properties of inductance 10, which depend on its topology, may be obtained.
To solve the stray capacitance problem, a solution consists of interposing a layer having a low dielectric coefficient between connecting track 29 and substrate 13 to draw them away from each other. For this purpose, connecting track 29 may be formed in the second metallization level, while spiral 20 is formed in the third metallization level.
However, such a configuration does not enable forming a continuous ground plane between spiral 20, then located on the third insulating layer, and tracks 22, 26, 40, and 32 of connection to other components or pads, located on the second and third insulating layers, which adversely affects the device performance, especially at high frequencies.